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<div class="title">xmbox_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga4f0eb6f00b1c4baf91576f2e6a32af87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga4f0eb6f00b1c4baf91576f2e6a32af87">XMbox_ReadReg</a>(BaseAddress, RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga4f0eb6f00b1c4baf91576f2e6a32af87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read one of the mbox registers.  <a href="group__mbox.html#ga4f0eb6f00b1c4baf91576f2e6a32af87">More...</a><br/></td></tr>
<tr class="separator:ga4f0eb6f00b1c4baf91576f2e6a32af87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga299c2eb6c04531a5da2202b9968531c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga299c2eb6c04531a5da2202b9968531c7">XMbox_WriteReg</a>(BaseAddress, RegOffset, ValueToWrite)&#160;&#160;&#160;Xil_Out32(((BaseAddress) + (RegOffset)), (ValueToWrite))</td></tr>
<tr class="memdesc:ga299c2eb6c04531a5da2202b9968531c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write a specified value to a register of a mbox.  <a href="group__mbox.html#ga299c2eb6c04531a5da2202b9968531c7">More...</a><br/></td></tr>
<tr class="separator:ga299c2eb6c04531a5da2202b9968531c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga267447e4cde5a2e0320ebba438c22a47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga267447e4cde5a2e0320ebba438c22a47">XMbox_WriteMBox</a>(BaseAddress, ValueToWrite)&#160;&#160;&#160;<a class="el" href="group__mbox.html#ga299c2eb6c04531a5da2202b9968531c7">XMbox_WriteReg</a> (BaseAddress, <a class="el" href="group__mbox.html#ga1cfe8987e8a70162381ff6893967fbd8">XMB_WRITE_REG_OFFSET</a>, ValueToWrite)</td></tr>
<tr class="memdesc:ga267447e4cde5a2e0320ebba438c22a47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write the mbox write register.  <a href="group__mbox.html#ga267447e4cde5a2e0320ebba438c22a47">More...</a><br/></td></tr>
<tr class="separator:ga267447e4cde5a2e0320ebba438c22a47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga20e3d2cc2c9ecc47fc1ce4420a8b69f8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga20e3d2cc2c9ecc47fc1ce4420a8b69f8">XMbox_ReadMBox</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__mbox.html#ga4f0eb6f00b1c4baf91576f2e6a32af87">XMbox_ReadReg</a> (BaseAddress, <a class="el" href="group__mbox.html#ga3a1f7a91d465c1e6be224c7f73d8ecea">XMB_READ_REG_OFFSET</a>)</td></tr>
<tr class="memdesc:ga20e3d2cc2c9ecc47fc1ce4420a8b69f8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the mbox read FIFO.  <a href="group__mbox.html#ga20e3d2cc2c9ecc47fc1ce4420a8b69f8">More...</a><br/></td></tr>
<tr class="separator:ga20e3d2cc2c9ecc47fc1ce4420a8b69f8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa533a34a21931e86fe66cbd144659b87"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gaa533a34a21931e86fe66cbd144659b87">XMbox_IsEmptyHw</a>(BaseAddress)&#160;&#160;&#160;((<a class="el" href="group__mbox.html#ga4f0eb6f00b1c4baf91576f2e6a32af87">XMbox_ReadReg</a> (BaseAddress, <a class="el" href="group__mbox.html#ga939d1f0b71e575a31a3689ca28cbc749">XMB_STATUS_REG_OFFSET</a>) &amp; <a class="el" href="group__mbox.html#gaa79d42f5c0e43f6b6679a42f119f9563">XMB_STATUS_FIFO_EMPTY</a>))</td></tr>
<tr class="memdesc:gaa533a34a21931e86fe66cbd144659b87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks if the Read FIFO is Empty.  <a href="group__mbox.html#gaa533a34a21931e86fe66cbd144659b87">More...</a><br/></td></tr>
<tr class="separator:gaa533a34a21931e86fe66cbd144659b87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga686ca5f4834e7e613350a2166cd49398"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga686ca5f4834e7e613350a2166cd49398">XMbox_IsFullHw</a>(BaseAddress)&#160;&#160;&#160;((<a class="el" href="group__mbox.html#ga4f0eb6f00b1c4baf91576f2e6a32af87">XMbox_ReadReg</a> (BaseAddress, <a class="el" href="group__mbox.html#ga939d1f0b71e575a31a3689ca28cbc749">XMB_STATUS_REG_OFFSET</a>) &amp; <a class="el" href="group__mbox.html#ga03cf0e55c079a09632583ac77df57329">XMB_STATUS_FIFO_FULL</a>))</td></tr>
<tr class="memdesc:ga686ca5f4834e7e613350a2166cd49398"><td class="mdescLeft">&#160;</td><td class="mdescRight">Checks if there is room in the Write FIFO.  <a href="group__mbox.html#ga686ca5f4834e7e613350a2166cd49398">More...</a><br/></td></tr>
<tr class="separator:ga686ca5f4834e7e613350a2166cd49398"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Offset Definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets within a mbox. </p>
</div></td></tr>
<tr class="memitem:ga1cfe8987e8a70162381ff6893967fbd8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga1cfe8987e8a70162381ff6893967fbd8">XMB_WRITE_REG_OFFSET</a>&#160;&#160;&#160;0x00</td></tr>
<tr class="memdesc:ga1cfe8987e8a70162381ff6893967fbd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox write register.  <a href="group__mbox.html#ga1cfe8987e8a70162381ff6893967fbd8">More...</a><br/></td></tr>
<tr class="separator:ga1cfe8987e8a70162381ff6893967fbd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3a1f7a91d465c1e6be224c7f73d8ecea"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga3a1f7a91d465c1e6be224c7f73d8ecea">XMB_READ_REG_OFFSET</a>&#160;&#160;&#160;0x08</td></tr>
<tr class="memdesc:ga3a1f7a91d465c1e6be224c7f73d8ecea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox read register.  <a href="group__mbox.html#ga3a1f7a91d465c1e6be224c7f73d8ecea">More...</a><br/></td></tr>
<tr class="separator:ga3a1f7a91d465c1e6be224c7f73d8ecea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga939d1f0b71e575a31a3689ca28cbc749"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga939d1f0b71e575a31a3689ca28cbc749">XMB_STATUS_REG_OFFSET</a>&#160;&#160;&#160;0x10</td></tr>
<tr class="memdesc:ga939d1f0b71e575a31a3689ca28cbc749"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox status reg.  <a href="group__mbox.html#ga939d1f0b71e575a31a3689ca28cbc749">More...</a><br/></td></tr>
<tr class="separator:ga939d1f0b71e575a31a3689ca28cbc749"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga777c199c53e918c3cbb896187ce28914"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga777c199c53e918c3cbb896187ce28914">XMB_ERROR_REG_OFFSET</a>&#160;&#160;&#160;0x14</td></tr>
<tr class="memdesc:ga777c199c53e918c3cbb896187ce28914"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox Error reg.  <a href="group__mbox.html#ga777c199c53e918c3cbb896187ce28914">More...</a><br/></td></tr>
<tr class="separator:ga777c199c53e918c3cbb896187ce28914"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabf6dc425ab72da28a9f30d37f803ec25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gabf6dc425ab72da28a9f30d37f803ec25">XMB_SIT_REG_OFFSET</a>&#160;&#160;&#160;0x18</td></tr>
<tr class="memdesc:gabf6dc425ab72da28a9f30d37f803ec25"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox send interrupt threshold register.  <a href="group__mbox.html#gabf6dc425ab72da28a9f30d37f803ec25">More...</a><br/></td></tr>
<tr class="separator:gabf6dc425ab72da28a9f30d37f803ec25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac1a7132725b8bd47cf0ddfa5e219a63a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gac1a7132725b8bd47cf0ddfa5e219a63a">XMB_RIT_REG_OFFSET</a>&#160;&#160;&#160;0x1C</td></tr>
<tr class="memdesc:gac1a7132725b8bd47cf0ddfa5e219a63a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox receive interrupt threshold register.  <a href="group__mbox.html#gac1a7132725b8bd47cf0ddfa5e219a63a">More...</a><br/></td></tr>
<tr class="separator:gac1a7132725b8bd47cf0ddfa5e219a63a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24776289ecaec70de8722b0d4e34db6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga24776289ecaec70de8722b0d4e34db6f">XMB_IS_REG_OFFSET</a>&#160;&#160;&#160;0x20</td></tr>
<tr class="memdesc:ga24776289ecaec70de8722b0d4e34db6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox interrupt status register.  <a href="group__mbox.html#ga24776289ecaec70de8722b0d4e34db6f">More...</a><br/></td></tr>
<tr class="separator:ga24776289ecaec70de8722b0d4e34db6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga992a83c0e5454de142ae0110531e6116"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga992a83c0e5454de142ae0110531e6116">XMB_IE_REG_OFFSET</a>&#160;&#160;&#160;0x24</td></tr>
<tr class="memdesc:ga992a83c0e5454de142ae0110531e6116"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox interrupt enable register.  <a href="group__mbox.html#ga992a83c0e5454de142ae0110531e6116">More...</a><br/></td></tr>
<tr class="separator:ga992a83c0e5454de142ae0110531e6116"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40250159d7755332fc0e4149b46985d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga40250159d7755332fc0e4149b46985d7">XMB_IP_REG_OFFSET</a>&#160;&#160;&#160;0x28</td></tr>
<tr class="memdesc:ga40250159d7755332fc0e4149b46985d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox interrupt pending register.  <a href="group__mbox.html#ga40250159d7755332fc0e4149b46985d7">More...</a><br/></td></tr>
<tr class="separator:ga40250159d7755332fc0e4149b46985d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12aab471e30140e408a6e9c396b44257"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga12aab471e30140e408a6e9c396b44257">XMB_CTRL_REG_OFFSET</a>&#160;&#160;&#160;0x2C</td></tr>
<tr class="memdesc:ga12aab471e30140e408a6e9c396b44257"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mbox control register.  <a href="group__mbox.html#ga12aab471e30140e408a6e9c396b44257">More...</a><br/></td></tr>
<tr class="separator:ga12aab471e30140e408a6e9c396b44257"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status register bit definitions</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>These status bits are used to poll the FIFOs </p>
</div></td></tr>
<tr class="memitem:gaa79d42f5c0e43f6b6679a42f119f9563"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gaa79d42f5c0e43f6b6679a42f119f9563">XMB_STATUS_FIFO_EMPTY</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gaa79d42f5c0e43f6b6679a42f119f9563"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO is Empty.  <a href="group__mbox.html#gaa79d42f5c0e43f6b6679a42f119f9563">More...</a><br/></td></tr>
<tr class="separator:gaa79d42f5c0e43f6b6679a42f119f9563"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga03cf0e55c079a09632583ac77df57329"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga03cf0e55c079a09632583ac77df57329">XMB_STATUS_FIFO_FULL</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga03cf0e55c079a09632583ac77df57329"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send FIFO is Full.  <a href="group__mbox.html#ga03cf0e55c079a09632583ac77df57329">More...</a><br/></td></tr>
<tr class="separator:ga03cf0e55c079a09632583ac77df57329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga12ee4cdd2f16e453fc3acca51768fb30"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga12ee4cdd2f16e453fc3acca51768fb30">XMB_STATUS_STA</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga12ee4cdd2f16e453fc3acca51768fb30"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send FIFO Threshold Status.  <a href="group__mbox.html#ga12ee4cdd2f16e453fc3acca51768fb30">More...</a><br/></td></tr>
<tr class="separator:ga12ee4cdd2f16e453fc3acca51768fb30"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5961a437539596663a0f87843d6f04d7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga5961a437539596663a0f87843d6f04d7">XMB_STATUS_RTA</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga5961a437539596663a0f87843d6f04d7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO Threshold Status.  <a href="group__mbox.html#ga5961a437539596663a0f87843d6f04d7">More...</a><br/></td></tr>
<tr class="separator:ga5961a437539596663a0f87843d6f04d7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Registers(s) bits definitions.</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>The IS, IE, and IP registers all have the same bit definition. </p>
</div></td></tr>
<tr class="memitem:ga03584ed8fe52cb5f04450bec96f00e51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga03584ed8fe52cb5f04450bec96f00e51">XMB_IX_STA</a>&#160;&#160;&#160;0x01</td></tr>
<tr class="memdesc:ga03584ed8fe52cb5f04450bec96f00e51"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send Threshold Active, when the number of Send FIFO entries is less than and equal to Send Interrupt Threshold.  <a href="group__mbox.html#ga03584ed8fe52cb5f04450bec96f00e51">More...</a><br/></td></tr>
<tr class="separator:ga03584ed8fe52cb5f04450bec96f00e51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4ca917f4f31be7e899e1adaa4c503aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gac4ca917f4f31be7e899e1adaa4c503aa">XMB_IX_RTA</a>&#160;&#160;&#160;0x02</td></tr>
<tr class="memdesc:gac4ca917f4f31be7e899e1adaa4c503aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive Threshold Active, when the number of Receive FIFO entries is greater than Receive Interrupt Threshold.  <a href="group__mbox.html#gac4ca917f4f31be7e899e1adaa4c503aa">More...</a><br/></td></tr>
<tr class="separator:gac4ca917f4f31be7e899e1adaa4c503aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad879d5982bf753dcf27efc6bb8cca604"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gad879d5982bf753dcf27efc6bb8cca604">XMB_IX_ERR</a>&#160;&#160;&#160;0x04</td></tr>
<tr class="memdesc:gad879d5982bf753dcf27efc6bb8cca604"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mailbox Error, when read on empty or write on full.  <a href="group__mbox.html#gad879d5982bf753dcf27efc6bb8cca604">More...</a><br/></td></tr>
<tr class="separator:gad879d5982bf753dcf27efc6bb8cca604"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Error bits definition.</div></td></tr>
<tr class="memitem:ga1fc712eb56bcc330c46c5bfe3f3c1583"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga1fc712eb56bcc330c46c5bfe3f3c1583">XMB_ERROR_FIFO_EMPTY</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga1fc712eb56bcc330c46c5bfe3f3c1583"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive FIFO is Empty.  <a href="group__mbox.html#ga1fc712eb56bcc330c46c5bfe3f3c1583">More...</a><br/></td></tr>
<tr class="separator:ga1fc712eb56bcc330c46c5bfe3f3c1583"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga90d8c6add066bca7fc234e0908a2ab56"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga90d8c6add066bca7fc234e0908a2ab56">XMB_ERROR_FIFO_FULL</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga90d8c6add066bca7fc234e0908a2ab56"><td class="mdescLeft">&#160;</td><td class="mdescRight">Send FIFO is Full.  <a href="group__mbox.html#ga90d8c6add066bca7fc234e0908a2ab56">More...</a><br/></td></tr>
<tr class="separator:ga90d8c6add066bca7fc234e0908a2ab56"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control register bits definition.</div></td></tr>
<tr class="memitem:ga9d015e11c5da1e44ab58be839cdf33d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#ga9d015e11c5da1e44ab58be839cdf33d3">XMB_CTRL_RESET_SEND_FIFO</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga9d015e11c5da1e44ab58be839cdf33d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Send FIFO.  <a href="group__mbox.html#ga9d015e11c5da1e44ab58be839cdf33d3">More...</a><br/></td></tr>
<tr class="separator:ga9d015e11c5da1e44ab58be839cdf33d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf8e2e5c1013346efd30bf5ea7314ebd7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__mbox.html#gaf8e2e5c1013346efd30bf5ea7314ebd7">XMB_CTRL_RESET_RECV_FIFO</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaf8e2e5c1013346efd30bf5ea7314ebd7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear Receive FIFO.  <a href="group__mbox.html#gaf8e2e5c1013346efd30bf5ea7314ebd7">More...</a><br/></td></tr>
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